1. Field of Invention
The invention relates to processes and substructures arising in the manufacture of integrated circuits and, more particularly, to processes, materials and substructures for reducing the critical dimensions of integrated circuit features.
2. Description of the Prior Art
Reducing the critical dimensions (“CDs”) of integrated circuit features is an important problem in the continuing efforts to increase the functionality of integrated circuits (“ICs”). Several lines of attack are possible. Reducing CDs by improving the mechanical and/or optical performance of photolithography requires improvement of mechanical steppers as well as improved printing (exposing and developing). Improving mechanical steppers can be economically problematic, requiring abandonment of existing steppers and loss of the capital investment.
Improved printing typically includes the use of exposing radiation with shorter wavelengths. Present IC photolithography systems typically use deep ultraviolet (“DUV”) radiation with a wavelength of 248 nm (nm=nanometer=10−9 meter), conveniently obtained from KrF excimer lasers. More advanced systems make use of ArF excimer lasers with a wavelength of 193 nm. However, the use of even shorter wavelengths (such as the F2 laser with a wavelength of 157 nm) is handicapped by the lack of suitable optical materials from which lenses or other optical components can be manufactured. In summary, improving photolithography by the use of shorter wavelengths involves both the financial burden of investment in replacement photolithography equipment and meeting the technical challenges of manipulating very short wavelengths.
Techniques have been described for reducing the CDs achievable with existing steppers and photolithography systems. That is, CD reduction is obtained by additional and/or different processing steps making use of presently-employed steppers and photolithography. CD reduction by the use of amorphous silicon spacer layers has been described by Kook et al (U.S. Pat. No. 6,008,123). However, it is often necessary to remove the hardmasks, spacers or other layers deposited to facilitate feature fabrication. Amorphous silicon belongs to a class of materials that are removable only with difficulty. Chemical mechanical planarization (“CMP”) is required to remove the materials described by Kook, which requires relatively expensive consumables and processing. Therefore, reducing CDs by means of materials removable by less expensive processing than CMP would simplify IC manufacturing and reduce costs.
Thus, a need exists in the art for achieving a reduction in CDs while avoiding the expense of CMP.